Software-based circuit design tools, also referred to as electronic design automation (EDA) tools or computer aided design (CAD) tools are capable of performing various circuit design-related tasks and circuit simulation functions. Circuit designs typically are specified in a programmatic form, i.e., using a hardware description language such as VHDL or Verilog. Hardware description languages permit hardware designers to define signals at a very high level of abstraction which can be translated, by a design tool, into actual pins and circuitry for a target device such as a programmable logic device (PLD). A design tool further can perform an analysis of the circuit design with respect to timing, functionality, and power consumption, as well as provide such information back to the circuit designer in one form or another, i.e., through some sort of visual display.
PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks, configurable logic blocks, dedicated random access memory blocks, multipliers, digital signal processing blocks, processors, clock managers, delay lock loops, digital frequency synthesizers (DFSs), and so forth.
In performing analysis on a given circuit design, a design tool relies upon a model for each of the various circuit elements found within the circuit design. Each model provides a procedure, or technique, for estimating the behavior of the circuit element to which the model corresponds. Thus, the design tool can determine information such as the output, power consumption, timing characteristics, and the like with respect to individual circuit elements as well as the circuit design as a whole.
In illustration, a DFS circuit element can provide an output signal having a frequency that is a function of the frequency of the input signal. An example of a DFS circuit element is the DFS circuit element available within the Virtex family of FPGA devices produced by Xilinx, Inc. of San Jose, Calif. (Xilinx and Virtex are registered trademarks of Xilinx, Inc.) This device can provide an output frequency that is determined by the expression FOut=FInM/D, where M and D are user-specified attributes. Ideally, each period of the output signal from the DFS circuit element is exactly the same as any other period of the output signal. The real behavior of the DFS circuit element, however, tends to exhibit a given amount of jitter. That is, each period of the output signal likely varies from the ideal period by a small amount. The amount of jitter found in the output signal of the DFS circuit element can be expressed as peak-to-peak jitter, also referred to as P2P.
Accurately estimating P2P for a DFS can influence circuit design decisions throughout the design process and further help to increase the chance of design success. Within a design tool, if an estimate of P2P is needed, the information typically is obtained by referencing a database comprising a vast amount of jitter data. Such a database tends to be large as the data reflects jitter measurements made across the entire range of possible input frequencies and for all possible combinations of values for M and D that may be used. Storing such a large volume of data requires significant memory resources, which can increase the amount of time used by a design tool to process such data and analyze a circuit design. Further, utilizing this data within a design tool in an effective manner can be a complex undertaking in and of itself.